S29NS-J Datasheet, PDF (22/85 Pages) SPANSION – 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories

Data Sheet
The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at
V_CC ± 0.2 V. The device requires standard access time (t_CE) for read access when the device is in
either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.
I_CC3 in the DC Characteristics table represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enters this mode when addresses remain stable for t_ACC + 60 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always
available to the system. I_CC4 in the DC Characteristics table represents the automatic sleep mode
current specification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t_RP, the device immediately terminates any
operation in progress, tristates all outputs, and ignores all read/write commands for the duration
of the RESET# pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V_SS±0.2 V, the
device draws CMOS standby current (I_CC4). If RESET# is held at V_IL but not within V_SS±0.2 V, the
standby current will be greater.
RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the device requires a time of t_READYW
(during Embedded Algorithms) before the device is ready to read data again. If RESET# is as-
serted when a program or erase operation is not executing, the reset operation is completed
within a time of t_READY (not during Embedded Algorithms). The system can read data t_RH after
RESET# returns to V_IH.
Refer to the AC Characteristics tables for RESET# parameters and to 14 for the timing diagram.
V_CC Power-up and Power-down Sequencing
The device imposes no restrictions on V_CC power-up or power-down sequencing. Asserting RE-
SET# to V_IL is required during the entire V_CC power sequence until the respective supplies reach
their operating voltages. Once V_CC attains its operating voltage, de-assertion of RESET# to V_IH is
permitted.
Output Disable Mode
When the OE# input is at V_IH, output from the device is disabled. The outputs are placed in the
high impedance state.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes (refer to Table 18 for command definitions).
The device offers three types of data protection at the sector level:
18
S29NS-J
S29NS-J_00_A10 March 22, 2006