S29NS-J Datasheet, PDF (21/85 Pages) SPANSION – 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories

Data Sheet
Handshaking Feature
The handshaking feature allows the host system to simply monitor the RDY signal from the device
to determine when the initial word of burst data is ready to be read. The host system should use
the wait state command sequence to set the number of wait states for optimal burst mode oper-
ation (03h for 54 and 66 MHz clock). The initial word of burst data is indicated by the rising edge
of RDY after OE# goes low.
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing
in one of the other three banks of memory. An erase operation may also be suspended to read
from or program to another location within the same bank (except the sector being erased). Fig-
ure 24 shows how read and write cycles may be initiated for simultaneous operation with zero
latency. Refer to the DC Characteristics table for read-while-program and read-while-erase cur-
rent specifications.
Writing Commands/Command Sequences
The device has inputs/outputs that accept both address and data information. To write a com-
mand or command sequence (which includes programming data to the device and erasing sectors
of memory), the system must drive AVD# and CE# to V_IL, and OE# to V_IH when providing an
address to the device, and drive WE# and CE# to V_IL, and OE# to V_IH. when writing commands
or data.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of
four.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 7 indicates
the address space that each sector occupies. The device address space is divided into four banks:
Bank A contains both 8 Kword boot sectors in addition to 32 Kword sectors, while Banks B, C, and
D contain only 32 Kword sectors. A “bank address” is the address bits required to uniquely select
a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector.
Refer to the DC Characteristics table for write mode current specifications. The AC Characteristics
section contains timing specification tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the A_cc input. This function is primarily
intended to allow faster manufacturing throughput at the factory. If the system asserts V_ID on
this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the
higher voltage on the input to reduce the time required for program operations. The system would
use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing
V_ID from the A_cc input returns the device to normal operation.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode.
The system can then read autoselect codes from the internal register (which is separate from the
memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Au-
toselect Functions and Autoselect Command Sequence sections for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input.
March 22, 2006 S29NS-J_00_A10
S29NS-J
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