S6E2HG Datasheet, PDF (42/161 Pages) SPANSION – fpu built-in

S6E2HG Series
Pin
Function
CAN0
CAN1
Reset
Mode
Power
GND
Clock
ADC
Power
VBAT
Power
ADC
GND
C pin
Pin Name
TX0_0
TX0_1
TX0_2
RX0_0
RX0_1
RX0_2
TX1_0
TX1_1
TX1_2
RX1_0
RX1_1
RX1_2
INITX
MD1
MD0
VCC
VSS
X0
X1
X0A
X1A
CROUT_0
CROUT_1
AVCC
AVRL
AVRH
VBAT
AVSS
C
Function Description
CAN interface ch.0 TX output pin
CAN interface ch.0 RX input pin
CAN interface ch.1 TX output pin
CAN interface ch.1 RX input pin
External Reset Input pin.
A reset is valid when INITX=L.
Mode 1 pin.
During serial programming to Flash
memory, MD1=L must be input.
Mode 0 pin.
During normal operation, MD0=L must be
input. During serial programming to Flash
memory, MD0=H must be input.
Power supply Pin
GND Pin
Main clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) input pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock output
port
A/D converter and D/A converter
analog power supply pin
A/D converter analog reference voltage
input pin
A/D converter analog reference voltage
input pin
VBAT power supply pin.
Backup power supply (battery etc.) and
system power supply.
A/D converter and D/A converter
GND pin
Power supply stabilization capacity pin
LQFP
120
51
18
114
52
19
113
84
12
63
85
11
62
Pin No
LQFP LQFP
100 80
-
-
13
-
94
74
-
-
14
-
93
73
-
-
-
-
53
42
-
-
-
-
52
41
38
33
23
56
46
36
57
47
37
1
1
1
31
26
-
46
41
31
61
51
-
91
76
61
117 97
77
107 92
-
30
25
20
45
40
30
60
50
40
90
75
60
120 100 80
-
-
-
58
48
38
59
49
39
39
34
24
40
35
25
87
72
58
113 93
73
70
60
49
72
62
51
73
63
52
43
38
28
71
61
50
44
39
29
FBGA
121
H6
F1
C3
H7
G1
B4
C9
G5
H10
B10
F6
J10
L3
L8
K9
B1
K1
K7
K11
A10
A4
A6
L1
L7
L11
A11
A1
K10
L9
L10
L4
K4
C10
B4
J11
G11
F11
L5
H11
L6
Document Number: 001-98943 Rev. *A
Page 42 of 161