S6E2HG Datasheet, PDF (3/161 Pages) SPANSION – fpu built-in

S6E2HG Series
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time Clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute/Second/A day of the week.) is
available. This function is also available by specifying only
Year, Month, Day, Hour or Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC)
(Max 3 channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
 Free-running
Periodic (=Reload)
 One-shot
Watch Counter
The Watch counter is used for wake up from the low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in high-speed CR clock or built-in low-speed CR
clock as the clock source.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
External Interrupt Controller Unit
External interrupt input pin: Max 16 pins
 Both edges(Rise edge and Fall edge) detect
Include one non-maskable interrupt (NMI)
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
Document Number: 001-98943 Rev. *A
This series consists of two different watchdogs, a Hardware
watchdog and a Software watchdog.
Hardware watchdog timer is clocked by low-speed internal CR
oscillator. Therefore, Hardware watchdog is active in any
power saving mode except Stop.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
SD Card Interface
It is possible to use the SD card that conforms to the following
standards.
Part 1 Physical Layer Specification version 3.01
Part E1 SDIO Specification version 3.00
Part A2 SD Host Controller Standard Specification version
3.00
1-bit or 4-bit data bus
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
Main clock: 4 MHz to 48 MHz
Sub Clock: 32.768 kHz
High-speed internal CR Clock: 4 MHz
Low-speed internal CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
Clock SuperVisor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
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