S6E2HG Datasheet, PDF (142/161 Pages) SPANSION – fpu built-in

S6E2HG Series
High-Speed Mode
Clock CLK (All values are referred to VIH and VIL)
Parameter
Clock frequency Data Transfer Mode
Clock low time
Clock high time
Clock rising time
Clock falling time
Symbol
fPP
tWL
tWH
tTLH
tTHL
Pin Name
S_CLK
S_CLK
S_CLK
S_CLK
S_CLK
Conditions
CCARD ≤ 10 pF
(1 card)
Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Input set-up time
tISU
Input hold time
tIH
Pin Name
S_CMD,
S_DATA3:0
S_CMD,
S_DATA3:0
Conditions
CCARD ≤ 10 pF
(1 card)
Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin Name
Output Delay time during Data
Transfer Mode
tODLY
S_CMD,
S_DATA3:0
Output Hold time
tOH
S_CMD,
S_DATA3:0
Total System capacitance for each
line*
CL
-
*: In order to satisfy severe timing, host shall drive only one card.
Conditions
CL ≤ 40 pF
(1 card)
CL ≥ 15 pF
(1 card)
1 card
(VCC = 2.7V to 3.6V, VSS = 0V)
Value
Min
Max
Remarks
0
32
MHz
7
-
ns
7
-
ns
-
3
ns
-
3
ns
Value
Min
Max
8
-
2
-
Remarks
ns
ns
Value
Min
Max
-
22
2.5
-
-
40
Remarks
ns
ns
pF
S_CLK
(SD Clock)
S_CMD,
S_DATA3:0
(Card Input)
S_CMD,
S_DATA3:0
(Card Output)
tWL
tWH
50%VCC ^VIH
VIL
VIL
VIH _50%VCC
VIH
tTHL
tISU
tTLH
tIH
VIH
VIH
tODLY(Max)
VIL
VIL
tOH(Min)
VOH
VOH
VOL
VOL
High-Speed Mode
Notes:
− The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the
Host.
− In high-speed mode, set the Clock frequency (fPP) and the AHB Bus Clock frequency to the same values.
Document Number: 001-98943 Rev. *A
Page 142 of 161