S6E2HG Datasheet, PDF (138/161 Pages) SPANSION – fpu built-in

S6E2HG Series
Fast Mode Plus (Fm+)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Fast(FMmo+d)e_*6Plus
Min
Max
Unit
Remarks
SCL clock frequency
fSCL
0
1000
kHz
(Repeated) Start condition hold time
SDA ↓ → SCL ↓
tHDSTA
0.26
-
μs
SCL clock L width
tLOW
0.5
-
μs
SCL clock H width
tHIGH
0.26
-
μs
(Repeated) Start condition setup time
SCL ↑ → SDA ↓
tSUSTA
0.26
-
μs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
CL = 30 pF,
R = (Vp/IOL)*¹
0
0.45*^2, *³
μs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
50
-
ns
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTO
0.26
-
μs
Bus free time between
Stop condition and
tBUF
Start condition
0.5
-
μs
60 MHz ≤
tCYCP<80 MHz
6 tCYCP*⁴
-
ns
80 MHz ≤
tCYCP<100 MHz
8 tCYCP*⁴
-
ns
Noise filter
tSP
100 MHz ≤
tCYCP<120 MHz
10 tCYCP*⁴
-
120 MHz ≤
tCYCP<140 MHz
12 tCYCP*⁴
-
ns
ns
*5
140 MHz ≤
tCYCP<160 MHz
14 tCYCP*⁴
-
ns
160 MHz ≤
tCYCP<180 MHz
16 tCYCP*⁴
-
ns
1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
2: The maximum tHDDAT must not extend beyond the low period (tLOW) of the device’s SCL signal.
3: The Fast mode I²C bus device can be used on a Standard-mode I²C bus system as long as the device satisfies the
requirement of tSUDAT ≥ 250 ns.”
4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I²C is connected, see
8.Block Diagram in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB
bus clock frequency.
6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I²C Fm+ in the EPFR register.
See Chapter 12: I/O Port in FM4 Family Peripheral Manual Main Part (MN709-00001) for the details.
Document Number: 001-98943 Rev. *A
Page 138 of 161