S6E2HG Datasheet, PDF (125/161 Pages) SPANSION – fpu built-in

S6E2HG Series
When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol Conditions
VCC < 4.5 V
Min
Max
VCC ≥ 4.5 V
Min
Max
Unit
SCS↓→SCK↓setup time
tCSSI
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
SCK↑→SCS↑ hold time
SCS deselect time
tCSHI
Internal shift
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
tCSDI
clock operation
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
SCS↓→SCK↓setup time
tCSSE
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
External shift
clock operation
3tCYCP+15
-
3tCYCP+15
-
ns
SCS↓→SOT delay time
tDSE
-
25
-
25
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family PERIPHERAL MANUAL.
− When the external load capacitance CL = 30 pF.
Document Number: 001-98943 Rev. *A
Page 125 of 161