SI53313 Datasheet, PDF (8/33 Pages) Silicon Laboratories – DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL TRANSLATOR

Si53313
Table 11. Additive Jitter, Differential Clock Input
V_DD
Input^1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)³
Freq Clock Format Amplitude
Differential Clock Format
Typ
Max
(MHz)
V_IN
20%-80% Slew
(Single-Ended, ^{Rate (V/ns)}
Peak-to-Peak)
3.3
725
Differential
0.15
0.637
LVPECL
45
65
3.3
725
Differential
0.15
0.637
LVDS
50
65
3.3 156.25 Differential
0.5
0.458
LVPECL
160
185
3.3 156.25 Differential
0.5
0.458
LVDS
150
200
2.5
725
Differential
0.15
0.637
LVPECL
45
65
2.5
725
Differential
0.15
0.637
LVDS
50
65
2.5 156.25 Differential
0.5
0.458
LVPECL
145
185
2.5 156.25 Differential
0.5
0.458
LVDS
145
195
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. AC-coupled differential inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 2.
CLK SYNTH
SMA103A
Low-Jitter
Clock Source
PSPL 5310A
Balun
CLKx
Si53313
50
DUT
50
CLKx
PSPL 5310A
Balun
AG E5052 Phase Noise
Analyzer
50 ohm
Figure 1. Differential Measurement Method Using a Balun
Important: See AN925 for additional information on the dependence of measured additive jitter on the input source jitter.
8
Rev. 1.0