SI53313 Datasheet, PDF (25/33 Pages) Silicon Laboratories – DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL TRANSLATOR

Pin #
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Name
Q0
Q0
NC
VDD
NC
CLK0
CLK0
OEA
V_REF
OEB
CLK1
CLK1
NC
GND
NC
Q9
Q9
Q8
Q8
NC
Q7
Si53313
Table 24. Pin Description (Continued)
Output clock 0 (complement)
Description
Output clock 0
No connect
Core voltage supply
Bypass with 1.0 µF capacitor placed as close to the VDD pin as possible
No connect
Input clock 0
Input clock 0 (complement)
When the CLK0 is driven by a single-end LVCMOS input, connect CLK0 to VDD/2.
Output enable—Bank A
When OE = high, the Bank A outputs are enabled
When OE = low, Q is held low and Q is held high for differential formats
For LVCMOS, both Q and Q are held low when OE is set low
OEA contains an internal pull-up resistor
Reference voltage for single-ended CMOS clocks.
V_REF is an output voltage and is equal to V_DD/2. It can be used to bias the /CLK input
for single ended input clocks. See "2.3. Voltage Reference (VREF)" on page 13.
Output enable—Bank B
When OE = high, the Bank B outputs are enabled
When OE = low, Q is held low and Q is held high for differential formats
For LVCMOS, both Q and Q are held low when OE is set low
OEB contains an internal pull-up resistor.
Input clock 1
Input clock 1 (complement)
When the CLK1 is driven by a single-end LVCMOS input, connect CLK1 to VDD/2.
No connect
Ground
No connect
Output clock 9 (complement)
Output clock 9
Output clock 8 (complement)
Output clock 8
No connect
Output clock 7 (complement)
Rev. 1.0
25