SI53313 Datasheet, PDF (13/33 Pages) Silicon Laboratories – DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL TRANSLATOR

Si53313
2.2. Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.
The non-inverting input is biased with a 18.75 k pulldown to GND and a 75 k pullup to V_DD. The inverting input
is biased with a 75 k pullup to V_DD.
V_DD
R_PU
R_PU
+
R_PD
CLK0 or
CLK1
–
R_PU = 75 kohm
R_PD = 18.75 kohm
Figure 6. Input Bias Resistors
2.3. Voltage Reference (V_REF)
The V_REF pin can be used to bias the input receiver, as shown in Figure 7 when a single-ended input clock (such
as LVCMOS) is used. Note that V_REF = V_DD/2 and should be compatible with the VCM rating of the single-ended
input clock driving the CLK0 or CLK1 inputs. To optimize jitter and duty cycle performance, use the circuit in
Figure 4. V_REF pin should be left floating when differential clocks are used.
V_DDO = 3.3 V, 2.5 V
Rs
CMOS Driver
Si53313
50
CLKx
CLKx
100 nF
V_REF
Figure 7. Using Voltage Reference with Single-Ended Input Clock
Rev. 1.0
13