SI53313 Datasheet, PDF (3/33 Pages) Silicon Laboratories – DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL TRANSLATOR

Si53313
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
T_A
V_DD
Test Condition
LVDS, CML
Min
Typ
Max Unit
–40
—
85
°C
1.71
1.8
1.89 V
2.38
2.5
2.63 V
2.97
3.3
3.63 V
LVPECL, low power LVPECL,
2.38
2.5
2.63 V
LVCMOS
2.97
3.3
3.63 V
HCSL
2.97
3.3
3.63 V
Output Buffer Supply
Voltage*
V_DDOX
LVDS, CML, LVCMOS
1.71
1.8
1.89 V
2.38
2.5
2.63 V
2.97
3.3
3.63 V
LVPECL, low power LVPECL
2.38
2.5
2.63 V
2.97
3.3
3.63 V
HCSL
2.97
3.3
3.63 V
*Note: Core supply V_DD and output buffer supplies V_DDO are independent. LVCMOS clock input is not supported for V_DD =
1.8V but is supported for LVCMOS clock output for V_DDOX = 1.8V. LVCMOS outputs at 1.5V and 1.2V can be
supported via a simple resistor divider network. See “2.8.1. LVCMOS Output Termination To Support 1.5 V and 1.2 V”
Table 2. Input Clock Specifications
(V_DD=1.8 V  5%, 2.5 V  5%, or 3.3 V  10%, T_A=–40 to 85 °C)
Parameter
Differential Input Com-
mon Mode Voltage
Differential Input Swing
(peak-to-peak)
LVCMOS Input High
Voltage
LVCMOS Input Low
Voltage
Input Capacitance
Symbol
Test Condition
V_CM
V_DD = 2.5 V 5%, 3.3 V 10%
V_IN
V_IH
V_DD = 2.5 V 5%, 3.3 V 10%
V_IL
V_DD = 2.5 V 5%, 3.3 V 10%
C_IN
CLK0 and CLK1 pins with
respect to GND
Min
0.05
0.2
V_DD x 0.7
—
—
Typ
Max Unit
—
—
V
—
2.2
V
—
—
V
— V_DD x 0.3 V
5
—
pF
Rev. 1.0
3