SI53313 Datasheet, PDF (26/33 Pages) Silicon Laboratories – DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL TRANSLATOR

Si53313
Pin #
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
GND
Pad
Name
Q7
SFOUTB[0]
SFOUTB[1]
DIVB
V_DDOB
Q6
Q6
Q5
Q5
GND
Q4
Q4
Q3
Q3
V_DDOA
GND
Table 24. Pin Description (Continued)
Output clock 7
Description
Output signal format control pin for Bank B
Three-level input control. Internally biased at VDD/2. Can be left floating or tied to
ground or V_DD.
Output signal format control pin for Bank B
Three-level input control. Internally biased at VDD/2. Can be left floating or tied to
ground or V_DD.
Output divider configuration bit for Bank B
Three-level input control. Internally biased at VDD/2. Can be left floating or tied to
ground or V_DD.
Output Clock Voltage Supply—Bank B (Outputs: Q5 to Q9)
Bypass with 1.0 µF capacitor and place close to the V_DDOB pin as possible
Output clock 6 (complement)
Output clock 6
Output clock 5 (complement)
Output clock 5.
Ground.
Output clock 4 (complement)
Output clock 4.
Output clock 3 (complement)
Output clock 3
Output Voltage Supply—Bank A (Outputs: Q0 to Q4)
Bypass with 1.0 µF capacitor and place close to the V_DDOA pin as possible
Ground Pad
Power supply ground and thermal relief
26
Rev. 1.0