SI53313 Datasheet, PDF (6/33 Pages) Silicon Laboratories – DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL TRANSLATOR

Si53313
Table 9. Output Characteristics—HCSL
(V_DDOX = 3.3 V ± 10%, T_A = –40 to 85 °C))
Parameter
Output Voltage High
Output Voltage Low
Single-Ended
Output Swing
Crossing Voltage
Symbol
V_OH
V_OL
V_SE
V_C
Test Condition
R_L = 50 Ω to GND
R_L = 50 Ω to GND
R_L = 50 Ω to GND
R_L = 50 Ω to GND
Min
Typ
Max
Unit
550
700
900
mV
–150
0
150
mV
450
700
850
mV
250
350
550
mV
Table 10. AC Characteristics
(V_DD = V_DDOX = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Frequency¹
Symbol
Test Condition
Min
F LVPECL, low power LVPECL, LVDS, dc
CML, HCSL
Typ Max Unit
—
1.25 GHz
Duty Cycle²
LVCMOS
dc
D_C
200 MHz, 20/80%T_R/T_F<10% of
40
period (LVCMOS)
(12 mA drive)
—
200 MHz
50
60
%
20/80% T_R/T_F<10% of period
(Differential)
47
50
53
%
Minimum Input Clock
Slew Rate³
SR
Required to meet prop delay and 0.75
—
additive jitter specifications
(20–80%)
—
V/ns
Output Rise/Fall Time
T_R/T_F
LVDS, 20/80%
LVPECL, 20/80%
HCSL⁴, 20/80%
—
—
325
ps
—
—
350
ps
—
—
280
ps
CML, 20/80%
—
—
350
ps
Low-Power LVPECL, 20/80%
LVCMOS 200 MHz, 20/80%,
2 pF load
—
—
325
ps
—
—
750
ps
Notes:
1. Slew rate should be >30 mV/ns.
2. 50% input duty cycle.
3. When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required.
4. HCSL measurements were made with receiver termination. See Figure 9 on page 17.
5. Output to Output skew specified for outputs with an identical configuration.
6. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
7. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DDOX (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
6
Rev. 1.0