SI53313 Datasheet, PDF (15/33 Pages) Silicon Laboratories – DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL TRANSLATOR

Si53313
2.5. Flexible Output Divider
The Si53313 provides optional clock division in addition to clock distribution. The divider setting for each bank of
output clocks is selected via 3-level control pins as shown in the table below. Leaving the DIVx pins open will force
a divider value of 1, which is the default mode of operation. Note that when using the on-chip clock divider, a
minimum input clock slew rate of 30 mV/ns is required.
Table 18. Divider Selection
DIVx*
Open
Divider Value
1 (default)
Frequency Range
dc to 1.25 GHz
0
2
dc to 725 MHz
1
4
dc to 725 MHz
*Note: DIVx are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin is
internally biased to V_DD/2.
2.6. Output Enable Logic
Each 1:5 output has an independent clock input (CLK0/CLK1) and an output enable pin. Table 19 summarizes the
input and output clock based upon the state of the input clock and the OE pin.
Table 19. Input Clock and Output Enable Logic
CLK
OE¹
Q²
L
H
L
H
H
H
X
L
L³
Notes:
1. Output enable active high.
2. On the next negative transition of CLK0 or CLK1.
3. Single-ended: Q = low, Q = low
Differential: Q = low, Q = high.
2.7. Power Supply (V_DD and V_DDOX)
The device includes separate core (V_DD) and output driver supplies (V_DDOX). This feature allows the core to
operate at a lower voltage than V_DDO, reducing current consumption in mixed supply applications. The core V_DD
supports 3.3 V, 2.5 V, or 1.8 V. Each output bank has its own V_DDOX supply, supporting 3.3 V, 2.5 V, or 1.8 V as
defined in Table 1 on page 3.
Rev. 1.0
15