SI5330 Datasheet, PDF (8/20 Pages) Silicon Laboratories – Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Si5330
Table 9. Absolute Maximum Ratings^1,2,3,4,5
Parameter
Symbol
Test Condition
Value
Unit
DC Supply Voltage
Storage Temperature Range
ESD Tolerance
V_DD
–0.5 to 3.8
V
T_STG
–55 to 150
°C
HBM
(100 pF, 1.5 k)
2.5
kV
ESD Tolerance
CDM
550
V
ESD Tolerance
MM
175
V
Latch-up Tolerance
JESD78 Compliant
Junction Temperature
Soldering Temperature
(Pb-free profile)⁵
T_J
T_PEAK
150
°C
260
°C
Soldering Temperature
(Pb-free profile)⁵
Time
at
T_PEAK
T_P
20–40
sec
Notes:
1. Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2. 24-QFN package is RoHS compliant.
3. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.
4. Moisture sensitivity level is MSL3.
5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
8
Rev. 1.0