SI5330 Datasheet, PDF (2/20 Pages) Silicon Laboratories – Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Si5330
1. Functional Block Diagrams Based on Orderable Part Number^*
1:4 Differential to Differential Buffer
Si5330A/B/C
IN1
IN2
IN3
LOS
OEB
Control
V_DDO0
CLK0A
CLK0B
VDDO1
CLK1A
CLK1B
VDDO2
CLK2A
CLK2B
VDDO3
CLK3A
CLK3B
1:8 Single-Ended to Single-Ended Buffer
Si5330F
IN3
IN1
IN2
LOS
OEB
Control
V_DDO0
CLK0A
CLK0B
VDDO1
CLK1A
CLK1B
VDDO2
CLK2A
CLK2B
VDDO3
CLK3A
CLK3B
1:8 Differential to Single-Ended Buffer 1:4 Single-Ended to Differential Buffer
Si5330G/H/J
IN1
IN2
IN3
LOS
OEB
Control
VDDO0
CLK0A
CLK0B
V_DDO1
CLK1A
CLK1B
V_DDO2
CLK2A
CLK2B
V_DDO3
CLK3A
CLK3B
Si5330K/L/M
IN3
IN1
IN2
LOS
OEB
Control
Figure 1. Si5330 Functional Block Diagrams
*Note: See Table 11 for detailed ordering information.
V_DDO0
CLK0A
CLK0B
V_DDO1
CLK1A
CLK1B
V_DDO2
CLK2A
CLK2B
V_DDO3
CLK3A
CLK3B
2
Rev. 1.0