SI5330 Datasheet, PDF (7/20 Pages) Silicon Laboratories – Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Si5330
Table 4. Input and Output Clock Characteristics (Continued)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
HSTL Output Voltage
Symbol
V_OH
V_OL
Duty Cycle^*
DC
*Note: Input clock has a 50% duty cycle.
Test Condition
VDDO = 1.4 to 1.6 V
Min
0.5xVDDO +0.3
—
45
Typ
Max
Units
—
—
V
—
0.5xVDDO
–0.3
V
—
55
%
Table 5. OEB Input Specifications
Parameter
Input Voltage Low
Input Voltage High
Input Resistance
Symbol
Test Condition
Min
Typ
Max
Unit
V_IL
—
—
0.3 x V_DD
V
V_IH
0.7 x V_DD
—
—
V
R_IN
20
—
—
k
Table 6. Output Control Pins (LOS)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Condition
Min
Typ
Max Unit
Output Voltage Low
Rise/Fall Time 20–80%
V_OL
I_SINK = 3 mA
0
t_R/t_F C_L < 10 pf, pull up 1 k
—
—
0.4
V
—
10
ns
Table 7. Jitter Specifications
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
Additive Phase Jitter
(12 kHz–20 MHz)
0.7 V pk-pk differential input
t_RPHASE clock at 622.08 MHz with
—
70 ps rise/fall time
Additive Phase Jitter
(50 kHz–80 MHz)
0.7 V pk-pk differential input
t_RPHASEWB clock at 622.08 MHz with
—
70 ps rise/fall time
Typ
0.150
0.225
Max
Unit
— ps RMS
— ps RMS
Table 8. Thermal Characteristics
Parameter
Thermal Resistance
Junction to Ambient
Thermal Resistance
Junction to Case
Symbol
_JA
_JC
Test Condition
Still Air
Still Air
Value
37
25
Unit
°C/W
°C/W
Rev. 1.0
7