SI5330 Datasheet, PDF (10/20 Pages) Silicon Laboratories – Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Si5330
5. Pin Descriptions
IN1
IN2
IN3
RSVD_GND
RSVD_GND
RSVD_GND
24 23 22 21 20 19
GND
GND
7 8 9 10 11 12
CLK1A
CLK1B
VDDO1
VDDO2
CLK2A
CLK2B
Note: Center pad must be tied to GND for normal operation.
Pin #
1
Pin Name
IN1
IN2
2
3
IN3
4
RSVD_GND
5
RSVD_GND
6
RSVD_GND
Table 10. Si5330 Pin Descriptions
I/O Signal Type
Description
I
Multi
Si5330A/B/C/G/H/J Differential Input Devices.
I
Multi
These pins are used as the differential clock input. IN1 is
the positive input; IN2 is the negative input. Refer to
“AN408: Termination Options for Any-Frequency, Any-
Output Clock Generators and Clock Buffers—Si5338,
Si5334, Si5330” for interfacing and termination details.
Si5330F/K/L/M Single-Ended Input Devices.
These pins are not used. Leave IN1 unconnected and
IN2 connected to ground.
Si5330F/K/L/M Single-Ended Devices.
This is the single-ended clock input. Refer to AN408 for
I
Multi
interfacing and termination details.
Si5330A/B/C/G/H/J Differential Input Devices.
This pin is not used. Connect to ground.
Ground.
Must be connected to system ground.
Ground.
Must be connected to system ground.
Ground.
Must be connected to system ground.
10
Rev. 1.0