SI5330 Datasheet, PDF (5/20 Pages) Silicon Laboratories – Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Si5330
Table 3. Performance Characteristics
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85°C)
Parameter
Symbol
Test Condition
Min Typ Max
Unit
CLKIN Loss of Signal Assert
Time
t_LOS
—
2.6
5
µs
CLKIN Loss of Signal De-Assert
Time
t_{LOS_B}
After initial start-up time has
expired
0.01
0.2
1
µs
Input-to-Output Propagation
Delay
t_PROP
—
2.5
4.0
ns
Output-Output Skew
t_DSKEW
Outputs at same signal
format
—
—
100
ps
POR to Output Clock Valid
t_START
Start-up time for output
clocks
—
—
2
ms
Table 4. Input and Output Clock Characteristics
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Input Clock (AC Coupled Differential Input Clocks on Pin IN1/2)
Frequency
f_IN
5
Differential Voltage Swing
V_PP
710 MHz input
0.4
Rise/Fall Time
Duty Cycle
t_R/t_F
20%–80%
—
DC
< 1 ns tr/tf
40
Input Impedance
R_IN
10
Input Capacitance
C_IN
—
Input Clock (DC-Coupled Single-Ended Input Clock on Pin IN3)
Frequency
CMOS
5
f_IN
HSTL, SSTL
5
Input Voltage
V_I
–0.1
Input Voltage Swing
(CMOS Standard)
200 MHz, Tr/Tf = 1.3 ns
0.8
Rise/Fall Time
Duty Cycle
t_R/t_F
20%–80%
—
DC
< 2 ns tr/tf
40
Input Capacitance
C_IN
—
Output Clocks (Differential)
Frequency
LVPECL, LVDS
5
f_OUT
HCSL
5
Typ
Max
Units
—
710
MHz
—
2.4
V_PP
—
1.0
ns
50
60
%
—
—
k
3.5
—
pF
—
200
MHz
—
350
MHz
—
VDD
V
—
—
Vpp
—
4
ns
50
60
%
2
—
pF
—
710
MHz
—
250
MHz
Rev. 1.0
5