SI5330 Datasheet, PDF(4/20 Page) Silicon Laboratories – Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

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SI5330 Datasheet, PDF (4/20 Pages) Silicon Laboratories – Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

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Si5330

2. Electrical Specifications

Table 1. Recommended Operating Conditions

(VDD = 1.8 V â5% to +10%, 2.5 V Â±10%, or 3.3 V Â±10%, TA = â40 to 85Â°C)

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

Ambient Temperature

â40

Â°C

2.97

3.3

3.63

Core Supply Voltage

VDD

2.25

2.5

2.75

1.71

1.8

1.98

Output Buffer Supply

Voltage

VDDOn

1.4

3.63

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 Â°C unless otherwise noted.

Table 2. DC Characteristics

(VDD = 1.8 V â5% to +10%, 2.5 V Â±10%, or 3.3 V Â±10%, TA = â40 to 85Â°C)

Parameter

Symbol

Test Condition

Min Typ Max

Unit

Core Supply Current

IDD

50 MHz refclk

LVPECL, 710 MHz

LVDS, 710 MHz

HCSL, 250 MHz

2 pF load capacitance

Output Buffer Supply Current

IDDOx

SSTL, 350 MHz

CMOS, 50 MHz

15 pF load capacitance

CMOS, 200 MHz

2 pF load capacitance

HSTL, 350 MHz

Rev. 1.0

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