SI5330 Datasheet, PDF (6/20 Pages) Silicon Laboratories – Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Si5330
Table 4. Input and Output Clock Characteristics (Continued)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
LVPECL Output Voltage
LVDS Output Voltage
(2.5/3.3 V)
LVDS Output Voltage
(1.8 V)
HCSL Output Voltage
Rise/Fall Time
Duty Cycle*
V_OC
V_SEPP
V_OC
V_SEPP
V_OC
V_SEPP
V_OC
V_SEPP
t_R/t_F
DC
Output Clocks (Single-Ended)
Frequency
CMOS 20%-80%
Rise/Fall Time
CMOS 20%-80%
Rise/Fall Time
CMOS Output
Resistance
SSTL Output Resistance
HSTL Output Resistance
CMOS Output Voltage
SSTL Output Voltage
f_OUT
t_R/t_F
t_R/t_F
V_OH
V_OL
V_OH
V_OL
V_OH
V_OL
V_OH
V_OL
common mode
peak-to-peak single-
ended swing
common mode
peak-to-peak single-
ended swing
common mode
peak-to-peak single-
ended swing
common mode
peak-to-peak single-
ended swing
20%–80%
CKn < 350 MHz
350 MHz < CLKn <
710 MHz
—
0.55
1.125
0.25
0.8
0.25
0.35
0.575
—
45
40
CMOS
5
SSTL, HSTL
5
2 pF load
—
15 pF load
—
—
—
—
4 mA load
VDDO–0.3
4 mA load
0.45xVDDO+0.41
SSTL-3 VDDOx = 2.97 to
3.63 V
—
0.5xVDDO+0.41
SSTL-2 VDDOx = 2.25 to
2.75 V
—
SSTL-18 VDDOx = 1.71
to 1.98 V
0.5xVDDO+0.34
—
Typ
V_DDO –
1.45 V
0.8
1.2
0.35
0.875
0.35
0.375
0.725
—
—
—
—
—
0.45
—
50
50
50
—
—
—
—
—
—
—
—
Max
Units
—
V
0.96
V_PP
1.275
V
0.45
V_PP
0.95
V
0.45
V_PP
0.400
V
0.85
V_PP
450
ps
55
%
60
%
200
MHz
350
MHz
0.85
ns
1.7
ns
—

—

—

V
0.3
V
—
V
0.45xVDDO
–0.41
V
—
V
0.5xVDDO–
0.41
V
V
0.5xVDDO–
0.34
V
6
Rev. 1.0