CP2110 Datasheet, PDF (8/26 Pages) Silicon Laboratories – SINGLE-CHIP HID USB TO UART BRIDGE

CP2110
3. Pinout and Package Definitions
Name
V_DD
Table 7. CP2110 Pin Definitions
–GM –GM1 Type
QFN24 QFN28
Description
6
6 Power In Power Supply Voltage Input.
Power Out Voltage Regulator Output. See Section 10.
V_IO
5
Power In I/O Supply Voltage Input.
Internally connected to V_DD on –GM1 packages.
GND
2
3
Ground. Must be tied to ground.
RST
9
REGIN
7
9
D I/O Device Reset. Open-drain output of internal POR or V_DD monitor. An
external source can initiate a system reset by driving this pin low for the
time specified in Table 4.
7 Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator.
VBUS
V_PP
D+
8
8
D In VBUS Sense Input. This pin should be connected to the VBUS signal of a
USB network.
16* 18* Special Connect 4.7 F capacitor between this pin and ground to support ROM
programming via the USB interface.
3
4
D I/O USB D+
D–
4
5
D I/O USB D–
TX
21
26
D Out Asynchronous data output (UART Transmit) for the UART Interface.
RX
20 25
D In Asynchronous data input (UART Receive) for the UART Interface.
GPIO.0 1*
2*
D I/O In GPIO mode, this pin is a user-configurable input or output.
CLK
GPIO.1 24* 24*
D Out In CLK mode, this pin outputs a configurable frequency clock signal.
D I/O In GPIO mode, this pin is a user-configurable input or output.
RTS
GPIO.2 23* 23*
D Out
D I/O
In hardware flow control mode, this pin is the Ready To Send control
output (active low) for the UART interface.
In GPIO mode, this pin is a user-configurable input or output.
CTS
GPIO.3 22* 1*
D In
D I/O
In hardware flow control mode, this pin is the Clear To Send control input
(active low) for the UART interface.
In GPIO mode, this pin is a user-configurable input or output.
RS485
D Out In RS-485 mode, this pin is the transmit active pin for the RS-485
transceiver.
*Note: Pins can be left unconnected when not used.
8
Rev. 1.2