CP2110 Datasheet, PDF (18/26 Pages) Silicon Laboratories – SINGLE-CHIP HID USB TO UART BRIDGE

CP2110
8. GPIO Pins
The CP2110 supports 10 user-configurable GPIO pins. Each of these GPIO pins are usable as inputs, open-drain
outputs, or push-pull outputs. Six of these GPIO pins also have alternate functions which are listed in Table 13.
More information regarding the configuration and usage of these pins is available in “AN721: CP21xx
Customization Guide” available on the Silicon Labs website.
Table 13. GPIO Pin Alternate Functions
GPIO Pin
GPIO.0
GPIO.1
GPIO.2
GPIO.3
GPIO.4
GPIO.5
Alternate Function
CLK Output
RTS
CTS
RS-485 Transceiver Control
TX Toggle
RX Toggle
The default configuration for all of the GPIO pins is provided in Table 14. The configuration of the pins is one-time
programmable for each device. See Section 9 for more information about programming the GPIO pin functionality.
Table 14. GPIO Pin Default Configuration
GPIO Pin
GPIO.0
GPIO.1
GPIO.2
GPIO.3
Default Function
GPIO Input
RTS
CTS
RS-485 Transceiver Control
GPIO Pin
GPIO.5
GPIO.6
GPIO.7
GPIO.8
Default Function
RX Toggle
GPIO Input
GPIO Input
GPIO Push-Pull Output
GPIO.4
TX Toggle
GPIO.9
GPIO Push-Pull Output
The difference between an open-drain output and a push-pull output is when the GPIO output is driven to logic
high. A logic high, open-drain output pulls the pin to the VIO rail through an internal, pull-up resistor. A logic high,
push-pull output directly connects the pin to the VIO voltage. Open-drain outputs are typically used when
interfacing to logic at a higher voltage than the VIO pin. These pins can be safely pulled to the higher, external
voltage through an external pull-up resistor. The maximum external pull-up voltage is 5 V.
The speed of reading and writing the GPIO pins is subject to the timing of the USB bus. GPIO pins configured as
inputs or outputs are not recommended for real-time signalling.
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