CP2110 Datasheet, PDF (19/26 Pages) Silicon Laboratories – SINGLE-CHIP HID USB TO UART BRIDGE

CP2110
8.1. GPIO.0—Clock Output
GPIO.0 is configurable to output a configurable CMOS clock output. The clock output appears at the pin at the
same time the device completes enumeration and exits USB Suspend mode. The clock output is removed from the
pin when the device enters USB Suspend mode. The output frequency is configurable through the use of a divider
and the accuracy is specified in Table 6. When the divider is set to 0, the output frequency is 24 MHz. For divider
values between 1 and 255, the output frequency is determined by the formula:
GPIO.0 Clock Frequency
=
-----²----⁴-----^M-----^H----^z------
2  Divider
Equation 4. GPIO.0 Clock Output Frequency
This divider is independent from the divider used to set UART baud rate.
8.2. GPIO.1-2—Hardware Flow Control (RTS and CTS)
By default, GPIO.1 and GPIO.2 are configured to operate as the hardware flow control pins RTS and CTS. In
addition to the GPIO PROM configuration, the device must be configured to use hardware flow control to use these
pins.
RTS, or Ready To Send, is an active-low output from the CP2110 and indicates to the external UART device that
the CP2110’s UART RX FIFO has not reached the watermark level of 450 bytes and is ready to accept more data.
When the amount of data in the RX FIFO reaches the watermark, the CP2110 pulls RTS high to indicate to the
external UART device to stop sending data.
CTS, or Clear To Send, is an active-low input to the CP2110 and is used by the external UART device to indicate to
the CP2110 when the external UART device’s RX FIFO is getting full. The CP2110 will not send more than two
bytes of data once CTS is pulled high.
CP2110
RS232
System
TX
RX
GPIO.1 – RTS
GPIO.2 – CTS
TX
RX
RTS
CTS
Figure 8. Hardware Flow Control Typical Connection Diagram
Rev. 1.2
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