CP2110 Datasheet, PDF (22/26 Pages) Silicon Laboratories – SINGLE-CHIP HID USB TO UART BRIDGE

CP2110
10. Voltage Regulator
The CP2110 includes an on-chip 5 to 3.45 V voltage regulator. This allows the CP2110 to be configured as either a
USB bus-powered device or a USB self-powered device. A typical connection diagram of the device in a bus-
powered application using the regulator is shown in Figure 11. When enabled, the voltage regulator output appears
on the V_DD pin and can be used to power external devices. See Table 5 for the voltage regulator electrical
characteristics.
If the regulator is used to provide V_DD in a self-powered application, use the same connections from Figure 11, but
connect REGIN to an on-board 5 V supply, and disconnect it from the VBUS pin. In addition, if REGIN may be un-
powered while VBUS is 5 V, a resistor divider shown in Note 5 of Figure 12 is required to meet the absolute
maximum voltage on VBUS specification in Table 1.
VIO ^{Note 3}
Note 1
3.3 V Power
1-5 F
0.1 F
VIO
VDD
CP2110
RST
SUSPEND
SUSPEND
VPP
4.7 k
Suspend
Signals
Note 4
4.7 F
USB
Connector
VBUS
D+
D-
GND
1 F
REGIN
GND
VBUS
D+
D-
Note 2
TX
RX
GPIO.0_CLK
GPIO.1_RTS
GPIO.2_CTS
GPIO.3_RS485
GPIO.4_TXT
GPIO.5_RXT
GPIO.6
GPIO.7
GPIO.8
GPIO.9
Standard
UART
and GPIO
Signals
Note 1 : VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface
voltage.
Note 2 : Avalanche transient voltage suppression diodes compatible with Full-speed USB should be
added at the connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.
Note 3 : An external pull-up is not required, but can be added for noise immunity.
Note 4 : If programming the configuration ROM via USB, add a 4.7 F capacitor between VPP
and ground. During a programming operation, do not connect the VPP pin to other
circuitry, and ensure that VDD is at least 3.3 V.
Figure 11. Typical Bus-Powered Connection Diagram
22
Rev. 1.2