CP2110 Datasheet, PDF (20/26 Pages) Silicon Laboratories – SINGLE-CHIP HID USB TO UART BRIDGE

CP2110
8.3. GPIO.3—RS-485 Transceiver Bus Control
GPIO.3 is configurable as an RS-485 bus transceiver control pin that is connected to the DE and RE inputs of the
transceiver. When configured for RS-485 mode, the pin is asserted during UART data transmission as well as line
break transmission. The RS-485 mode of GPIO.3 is active-high by default, but is also configurable for active-low
mode.
CP2110
RS485
Transceiver
TX
R
RX
D
GPIO.3 – RS485
RE
DE
Figure 9. RS-485 Transceiver Typical Connection Diagram
8.4. GPIO.4-5—Transmit and Receive Toggle
GPIO.4 and GPIO.5 are configurable as Transmit Toggle and Receive Toggle pins. These pins are logic high when
a device is not transmitting or receiving data, and they toggle at a fixed rate as specified in Table 6 when data
transfer is in progress. Typically, these pins are connected to two LEDs to indicate data transfer.
VIO
CP2110
GPIO.4 – TX Toggle
GPIO.5 – RX Toggle
Figure 10. Transmit and Receive Toggle Typical Connection Diagram
More information regarding the configuration and usage of these pins can be found in Section 9 as well as “AN721:
CP21xx Customization Guide” available on the Silicon Labs website.
20
Rev. 1.2