CP2110 Datasheet, PDF (23/26 Pages) Silicon Laboratories – SINGLE-CHIP HID USB TO UART BRIDGE

CP2110
Alternatively, if 3.0 to 3.6 V power is supplied to the V_DD pin, the CP2110 can function as a USB self-powered
device with the voltage regulator bypassed. For this configuration, tie the REGIN input to V_DD to bypass the voltage
regulator. A typical connection diagram showing the device in a self-powered application with the regulator
bypassed is shown in Figure 12.
The USB max power and power attributes descriptor must match the device power usage and configuration. See
application note “AN721: CP21xx Customization Guide” for information on how to customize USB descriptors for
the CP2110.
3.3 V
Power
Note 1
VIO
VDD
REGIN
CP2110
RST
SUSPEND
SUSPEND
VPP
VIO ^{Note 3}
4.7 k
Suspend
Signals
Note 4
4.7 F
1-5 F
0.1 F
Note 5
(Optional) ^{24 k}
USB
Connector
47 k
VBUS
D+
D-
GND
GND
VBUS
D+
D-
TX
RX
GPIO.0_CLK
GPIO.1_RTS
GPIO.2_CTS
GPIO.3_RS485
GPIO.4_TXT
GPIO.5_RXT
GPIO.6
GPIO.7
GPIO.8
GPIO.9
Standard
UART
and GPIO
Signals
Note 2
Note 1 : VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface
voltage.
Note 2 : Avalanche transient voltage suppression diodes compatible with Full-speed USB should be
added at the connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.
Note 3 : An external pull-up is not required, but can be added for noise immunity.
Note 4 : If programming the configuration ROM via USB, add a 4.7 F capacitor between VPP
and ground. During a programming operation, do not connect the VPP pin to other
circuitry, and ensure that VDD is at least 3.3 V.
Note 5 : For self-powered systems where VDD and VIO may be unpowered when VBUS is connected
to 5 V, a resistor divider (or functionally-equivalent circuit) on VBUS is required to meet the
absolute maximum voltage on VBUS specification in the Electrical Characteristics section.
Figure 12. Typical Self-Powered Connection Diagram (Regulator Bypass)
Rev. 1.2
23