SI53119-A03A Datasheet, PDF (7/34 Pages) Silicon Laboratories – PLL or bypass mode

Si53119-A03A
Table 5. Output Skew, PLL Bandwidth and Peaking
T_A = 0–70 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Test Condition
Min
Typ Max Unit
CLK_IN, DIF[x:0]
Input-to-Output Delay in PLL Mode
Nominal Value^1,2,3,4
–100
18
100
ps
CLK_IN, DIF[x:0]
Input-to-Output Delay in Bypass Mode
Nominal Value^2,4,5
2.5
3.6
4.5
ns
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in PLL mode
–50
20
50
ps
Over Voltage and Temperature^2,4,5
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in Bypass Mode –250
—
250
ps
Over Voltage and Temperature^2,4,5
DIF[11:0]
Output-to-Output Skew across all 19 Outputs
0
(Common to Bypass and PLL Mode)^1,2,3,4,5
20
50
ps
PLL Jitter Peaking
(HBW_BYPASS_LBW = 0)⁶
—
0.4
2.0
dB
PLL Jitter Peaking
(HBW_BYPASS_LBW = 1)⁶
—
0.1
2.5
dB
PLL Bandwidth
(HBW_BYPASS_LBW = 0)⁷
—
0.7
1.4 MHz
PLL Bandwidth
(HBW_BYPASS_LBW = 1)⁷
—
2
4
MHz
Notes:
1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the
corresponding input.
2. Measured from differential cross-point to differential cross-point.
3. This parameter is deterministic for a given device.
4. Measured with scope averaging on to find mean value.
5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created
by it.
6. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL
jitter peaking.
7. Measured at 3 dB down or half power point.
Rev. 1.0
7