SI53119-A03A Datasheet, PDF (5/34 Pages) Silicon Laboratories – PLL or bypass mode

Si53119-A03A
Table 2. SMBus Characteristics
Parameter
SMBus Input Low Voltage¹
SMBus Input High Voltage¹
SMBus Output Low Voltage¹
Nominal Bus Voltage¹
SMBus sink Current¹
SCLK/SDAT Rise Time¹
SCLK/SDAT Fall Time¹
SMBus Operating Frequency^1,2
Symbol
V_ILSMB
V_IHSMB
V_OLSMB
V_DDSMB
I_PULLUP
t_RSMB
t_FSMB
f_MINSMB
Test Condition
@ I_PULLUP
@ V_OL
3 V to 5 V +/-10%
(Max V_IL – 0.15) to (Min V_IH + 0.15)
(Min V_IH + 0.15) to (Max V_IL – 0.15)
Minimum Operating Frequency
Notes:
1. Guaranteed by design and characterization
2. The differential input clock must be running for the SMBus to be active
Min Max Unit
—
0.8
V
2.1 V_DDSMB V
0.4
V
2.7
5.5
V
4
—
mA
—
1000
ns
—
300
ns
100
—
kHz
Table 3. Current Consumption
T_A = 0–70 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Symbol
Test Condition
Min
Operating Current
IDD_VDD
100 MHz, VDD Rail, Zo=85
—
IDD_VDDA 100 MHz, VDDA + VDDR, PLL Mode, —
Zo=85
IDD_VDDIO 100 MHz, CL = Full Load, VDDIO Rail, —
Zo=85
Power Down Current IDD_VDDPD
Power Down, VDD Rail
—
IDD_VDDAPD
Power Down, VDDA Rail
—
IDD_VDDIOPD
Power Down, VDD_IO Rail
—
Typ
25
16
130
1.5
8
0.17
Max
35
20
150
2
12
0.5
Unit
mA
mA
mA
mA
mA
mA
Rev. 1.0
5