SI53119-A03A Datasheet, PDF (22/34 Pages) Silicon Laboratories – PLL or bypass mode

Si53119-A03A
Table 18. Byte 2: Output Enable Control Register
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
Output(s)
Affected
0
Output Enable DIF 8
Low/Low
Enabled
RW
1
DIF[8]
1
Output Enable DIF 9
Low/Low
Enabled
RW
1
DIF[9]
2
Output Enable DIF 10
Low/Low
Enabled
RW
1
DIF[10]
3
Output Enable DIF 11
Low/Low
Enabled
RW
1
DIF[11]
4
Output Enable DIF 12
Low/Low
Enabled
RW
1
DIF[112
5
Output Enable DIF 13
Low/Low
Enabled
RW
1
DIF[14]
6
Output Enable DIF 14
Low/Low
Enabled
RW
1
DIF[15]
7
Output Enable DIF 15
Low/Low
Enabled
RW
1
DIF[16
Table 19. Byte 3: Reserved Control Register
Bit
Description
If Bit = 0 If Bit = 1
Type
Default Output(s)
Affected
0
Reserved
0
1
Reserved
0
2
Reserved
0
3
Reserved
0
4
Reserved
0
5
Reserved
0
6
Reserved
0
7
Reserved
0
22
Rev. 1.0