SI53119-A03A Datasheet, PDF (18/34 Pages) Silicon Laboratories – PLL or bypass mode

Si53119-A03A
Skew measurement
point
0.000 V
High Duty Cycle %
TPeriod
Low Duty Cycle %
Figure 5. Differential (CLOCK–CLOCK) Measurement Points (T_period, Duty Cycle, Jitter)
3.2. Termination of Differential Outputs
All differential outputs are to be tested into an 85  differential impedance transmission line. All output termination
resistors are fully integrated into the Si53119-A03A, no external components are required. Contact Silicon Labs if
100 differential impedance support is needed.
Clock
Z0 = 85ohm, 10" Trace
Receiver
2 pF
2 pF
Clock #
Z0 = 85ohm, 10" Trace
Figure 6. 0.7 V Configuration Test Load Board Termination for NMOS Push-Pull
18
Rev. 1.0