SI53119-A03A Datasheet, PDF (14/34 Pages) Silicon Laboratories – PLL or bypass mode

Si53119-A03A
2.4. CKPWRGD/PWRDN
CKPWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to
indicating a power down condition. CKPWRGD (assertion) is used by the Si53119-A03A to sample initial
configurations, such as frequency select condition and SA selections. After CKPWRGD has been asserted high for
the first time, the pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and
instruct the device to invoke power-saving mode. PWRDN is a completely asynchronous active low input. When
entering power-saving mode, PWRDN should be asserted low prior to shutting off the input clock or power to
ensure all clocks shut down in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior
to turning off the VCO. When PWRDN is deasserted high, all clocks will start and stop without any abnormal
behavior and will meet all ac and dc parameters.
Note: The assertion and deassertion of PWRDN is absolutely asynchronous.
Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended. Oper-
ation in this mode may result in glitches, excessive frequency shifting, etc.
Table 13. CKPWRGD/PWRDN Functionality
CKPWRGD/
PWRDN
0
1
DIF_IN/
DINF_IN#
X
Running
SMBus
EN bit
X
0
1
DIF-x/
DIF_x#
Low/Low
Low/Low
Running
FBOUT_NC/
FBOUT_NC#
Low/Low
Running
Running
PLL State
OFF
ON
ON
2.4.1. PWRDN Assertion
When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held LOW/
LOW on the next DIF high-to-low transition.
PWRDWN
DIF
DIF
Figure 1. PWRDN Assertion
14
Rev. 1.0