SI53119-A03A Datasheet, PDF (15/34 Pages) Silicon Laboratories – PLL or bypass mode

Si53119-A03A
2.4.2. CKPWRGD Assertion
The powerup latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the assertion of
the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs
stopped in a LOW/LOW condition resulting from power down must be driven high in less than 300 µs of PWRDN
deassertion to a voltage greater than 200 mV.
PWRGD
DIF
Tstable
<1.8 ms
DIF
Tdrive_Pwrdn#
<300 µs; > 200 mV
Figure 2. PWRDG Assertion (Pwrdown—Deassertion)
2.5. HBW_BYPASS_LBW
The HBW_BYPASS_LBW pin is a tri-level function input pin (refer to Table 1 for VIL_Tri, VIM_Tri, and VIH_Tri
signal levels). It is used to select between PLL high-bandwidth, PLL bypass mode, or PLL low-bandwidth mode. In
PLL bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive
cycle-to-cycle jitter (50 ps + input jitter) on the differential outputs. In PLL mode, the input clock is passed through a
PLL to reduce high-frequency jitter. The PLL HBW, BYPASS, and PLL LBW modes may be selected by asserting
the HBW_BYPASS_LBW input pin to the appropriate level described in Table 14.
Table 14. PLL Bandwidth and Readback Table
HBW_BYPASS_LBW Pin
L
M
H
Mode
LBW
BYPASS
HBW
Byte 0, Bit 7
0
0
1
Byte 0, Bit 6
0
1
1
The Si53119-A03A has the ability to override the latch value of the PLL operating mode from hardware strap pin 5
via the use of Byte 0 and bits 2 and 1. Byte 0 bit 3 must be set to 1 to allow the user to change Bits 2 and 1,
affecting the PLL. Bits 7 and 6 will always read back the original latched value. A warm reset of the system will
have to be accomplished if the user changes these bits.
Rev. 1.0
15