SI53119-A03A Datasheet, PDF (27/34 Pages) Silicon Laboratories – PLL or bypass mode

Si53119-A03A
Table 24. Si53119-A03A 72-Pin QFN Descriptions
Pin #
1
2
3
Name
VDDA
GNDA
100M_133M
4 HBW_BYPASS_LBW
5
PWRGD/PWRDN
6
GND
7
VDDR
8
CLK_IN
9
CLK_IN
10
SA_0
11
SDA
12
SCL
13
SA_1
14
FBOUT / NC
15
FBOUT / NC
16
GND
17
DIF_0
18
DIF_0
19
DIF_1
20
DIF_1
21
VDD_IO
22
GND
23
DIF_2
24
DIF_2
Type
3.3 V
GND
I,SE
I, SE
I
GND
VDD
I, DIF
I, DIF
I,PU
I/O
I/O
I,PU
I/O
I/O
GND
O, DIF
O, DIF
O, DIF
O, DIF
VDD
GND
O, DIF
O, DIF
Description
3.3 V power supply for PLL.
Ground for PLL.
3.3 V tolerant inputs for input/output frequency selection. An external
pull-up or pull-down resistor is attached to this pin to select the input/
output frequency. Internal pullup.
High = 100 MHz output
Low = 133 MHz output
Tri-Level input for selecting the PLL bandwidth or bypass mode.
High = High BW mode
Med = Bypass mode
Low = Low BW mode
3.3 V LVTTL input to power up or power down the device.
Ground for outputs.
3.3 V power supply for differential input receiver. This VDDR should
be treated as an analog power rail and filtered appropriately.
0.7 V Differential input.
0.7 V Differential input.
3.3 V LVTTL input selecting the address. Tri-level input. Internal
pullup.
Open collector SMBus data.
SMBus slave clock input.
3.3 V LVTTL input selecting the address. Tri-level input. Internal
pullup.
Complementary differential feedback output. Do not connect this pin
to anything.
True differential feedback output. Do not connect this pin to anything.
Ground for outputs.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
Power supply for differential outputs.
Ground for outputs.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
Rev. 1.0
27