SI53119-A03A Datasheet, PDF (29/34 Pages) Silicon Laboratories – PLL or bypass mode

Pin #
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Si53119-A03A
Table 24. Si53119-A03A 72-Pin QFN Descriptions (Continued)
Name
DIF_12
DIF_13
DIF_13
VDD_IO
GND
DIF_14
DIF_14
DIF_15
DIF_15
GND
VDD
DIF_16
DIF_16
DIF_17
DIF_17
VDD_IO
GND
DIF_18
DIF_18
GND
Type
O, DIF
O, DIF
O, DIF
VDD
GND
O, DIF
O, DIF
O, DIF
O, DIF
GND
3.3 V
O, DIF
O, DIF
O, DIF
O, DIF
VDD
GND
O, DIF
O, DIF
GND
Description
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
Power supply for differential outputs.
Ground for outputs.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
Ground for outputs.
3.3 V power supply for outputs.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
Power supply for differential outputs.
Ground for outputs.
0.7 V Differential clock outputs. Default is 1:1.
0.7 V Differential clock outputs. Default is 1:1.
Ground for outputs.
Rev. 1.0
29