SI53312 Datasheet, PDF(3/33 Page) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

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SI53312 Datasheet, PDF (3/33 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

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Si53312

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Ambient Operating

Temperature

Supply Voltage Range*

Symbol

VDD

Test Condition

LVDS, CML

Min

Typ

Max Unit

â40

Â°C

1.71

1.8

1.89 V

2.38

2.5

2.63 V

2.97

3.3

3.63 V

LVPECL, low power LVPECL,

2.38

2.5

2.63 V

LVCMOS

2.97

3.3

3.63 V

HCSL

2.97

3.3

3.63 V

Output Buffer Supply

Voltage*

VDDOX

LVDS, CML, LVCMOS

1.71

1.8

1.89 V

2.38

2.5

2.63 V

2.97

3.3

3.63 V

LVPECL, low power LVPECL

2.38

2.5

2.63 V

2.97

3.3

3.63 V

HCSL

2.97

3.3

3.63 V

*Note: Core supply VDD and output buffer supplies VDDO are independent. LVCMOS clock input is not supported for VDD =

1.8V but is supported for LVCMOS clock output for VDDOX = 1.8V. LVCMOS outputs at 1.5V and 1.2V can be

supported via a simple resistor divider network. See â2.8.1. LVCMOS Output Termination To Support 1.5 V and 1.2 Vâ

Table 2. Input Clock Specifications

(VDD=1.8 V ï± 5%, 2.5 V ï± 5%, or 3.3 V ï± 10%, TA=â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Min

Typ

Max Unit

Differential Input Common VCM

Mode Voltage

VDD = 2.5 Vï± 5%, 3.3 Vï± 10%

0.05

Differential Input Swing

VIN

(peak-to-peak)

0.2

2.2

LVCMOS Input High

Voltage

VIH

VDD = 2.5 Vï± 5%, 3.3 Vï± 10% VDD x 0.7

LVCMOS Input Low

Voltage

VIL

VDD = 2.5 Vï± 5%, 3.3 Vï± 10%

VDD x V

0.3

Input Capacitance

CIN

CLK0 and CLK1 pins with

respect to GND

Rev. 1.0

▷