SI53312 Datasheet, PDF (26/33 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53312
Pin #
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Table 24. Si53312 44-Pin QFN Descriptions (Continued)
Name
Q0
Output clock 0 (complement).
Description
Q0
Output clock 0.
NC
No connect.
V_DD
Core voltage supply.
Bypass with a 1.0 µF capacitor placed as close to the pin as possible.
NC
No connect.
CLK0
Input clock 0.
CLK0
OEA
V_REF
OEB
CLK1
Input clock 0 (complement).
When the CLK0 is driven by a single-end LVCMOS input, connect CLK0 to Vdd/2.
CLK0 contains an internal pull-up resistor.
Output enable—Bank A.
When OEA = high, the Bank A outputs are enabled.
When OEA = low, Q is held low and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OEA is set low.
OEA contains an internal pull-up resistor.
Reference voltage for single-ended CMOS clocks.
V_REF is an output voltage and is equal to V_DD/2. It can be used to bias the /CLK input
for single ended input clocks. See Section 2.3 for more details.
Output enable—Bank B.
When OEB = high, the Bank B outputs are enabled.
When OEB = low, Q is held low and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OEB is set low.
OEB contains an internal pull-up resistor.
Input clock 1.
CLK1
NC
Input clock 1 (complement).
When the CLK1 is driven by a single-end LVCMOS input, connect CLK1 to Vdd/2.
CLK1 contains an internal pull-up resistor.
No connect.
GND
Ground.
CLK_SEL
Q9
MUX input select pin (LVCMOS).
When CLK_SEL is high, CLK1 is selected.
When CLK_SEL is low, CLK0 is selected.
CLK_SEL contains an internal pull-down resistor.
Output clock 9 (complement).
Q9
Output clock 9.
Q8
Output clock 8 (complement).
26
Rev. 1.0