SI53312 Datasheet, PDF (27/33 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53312
Pin #
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
GND
Pad
Table 24. Si53312 44-Pin QFN Descriptions (Continued)
Name
Q8
Output clock 8.
Description
NC
No connect.
Q7
Output clock 7 (complement).
Q7
Output clock 7.
SFOUTB[0]
SFOUTB[1]
DIVB
V_DDOB
Q6
Output signal format control pin for Bank B.
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
Output signal format control pin for Bank B.
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
Output divider configuration bit for Bank B.
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
Output Clock Voltage Supply—Bank B (Outputs: Q5 to Q9).
Bypass with a 1.0 µF capacitor placed as close to the pin as possible.
Output clock 6 (complement).
Q6
Output clock 6.
Q5
Output clock 5 (complement).
Q5
Output clock 5.
GND
Ground.
Q4
Output clock 4 (complement).
Q4
Output clock 4.
Q3
Output clock 3 (complement).
Q3
Output clock 3.
V_DDOA
GND
Output Voltage Supply—Bank A (Outputs: Q0 to Q4).
Bypass with a 1.0 µF capacitor placed as close to the pin as possible.
Ground Pad.
Power supply ground and thermal relief.
Rev. 1.0
27