SI53312 Datasheet, PDF (15/33 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53312
2.5. Input Mux and Output Enable Logic
The Si53312 provides two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the
input mux and output enable pin settings.
Table 18. Input Mux and Output Enable Logic
CLK_SEL CLK0
CLK1
OE¹
Q²
L
L
X
H
L
L
H
X
H
H
H
X
L
H
L
H
X
H
H
H
X
X
X
L
L³
Notes:
1. Output enable active high
2. On the next negative transition of CLK0 or CLK1.
3. Single-end: Q=low, Q=high
Differential: Q=low, Q=high
2.6. Flexible Output Divider
The Si53312 provides optional clock division in addition to clock distribution. The divider setting for each bank of
output clocks is selected via 3-level control pins as shown in the table below. Leaving the DIVx pins open will force
a divider value of 1, which is the default mode of operation. Note that when using the on-chip clock divider, a
minimum input clock slew rate of 30 mV/ns is required.
Table 19. Divider Selection
DIVx¹
Open²
0³
1³
Divider Value
1 (default)
2
4
Notes:
1. DIVx are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin is internally
biased to V_DD/2.
2. For frequency range dc to 1.25 GHz.
3. For frequency range dc to 725 MHz.
2.7. Power Supply (V_DD and V_DDOX)
The device includes separate core (V_DD) and output driver supplies (V_DDOX). This feature allows the core to
operate at a lower voltage than V_DDO, reducing current consumption in mixed supply applications. The core V_DD
supports 3.3, 2.5, or 1.8 V. Each output bank has its own V_DDOX supply, supporting 3.3, 2.5, or 1.8 V as defined in
Table 1.
Rev. 1.0
15