SI53312 Datasheet, PDF (11/33 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53312
2. Functional Description
The Si53312 is a low jitter, low skew 1:10 differential buffer with an integrated 2:1 input mux. The device has a
universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select
the active input clock. The selected clock input is routed to two independent banks of outputs. Each output bank
features control pins to select signal format, output enable, output divider setting and LVCMOS drive strength.
2.1. Universal, Any-Format Input
The Si53312 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including
LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various input ac- and dc-coupling
options supported by the device. Figures 3 and 4 show the recommended input clock termination options.
Table 15. LVPECL, LVCMOS, and LVDS
1.8 V
2.5/3.3 V
LVPECL
AC-Couple DC-Couple
N/A
N/A
Yes
Yes
LVCMOS
AC-Couple DC-Couple
No
No
No
Yes
LVDS
AC-Couple DC-Couple
Yes
No
Yes
Yes
1.8 V
2.5/3.3 V
Table 16. HCSL and CML
HCSL
AC-Couple DC-Couple
CML
AC-Couple DC-Couple
No
No
Yes
No
Yes
Yes (3.3 V)
Yes
No
0.1 µF
CLKx
Si53312
100 
/CLKx
0.1 µF
Figure 2. Differential LVPECL, LVDS, CML AC-Coupled Input Termination
VDDO _{= 3. 3 V or2. 5 V}
CMOS
Driver
Rs
VDD
1 k
VDD
CLKx
50
CLKx
VTERM = VDD/2
1 k
VREF
Si53312
Figure 3. LVCMOS DC-Coupled Input Termination
Rev. 1.0
11