SI53312 Datasheet, PDF (21/33 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53312
2.11. Typical Phase Noise Performance
Each of the following three figures shows three phase noise plots superimposed on the same diagram.
Source Jitter: Reference clock phase noise.
Total Jitter (SE): Combined source and clock buffer phase noise measured as a single-ended output to the phase
noise analyzer and integrated from 12 kHz to 20 MHz.
Total Jitter (Diff): Combined source and clock buffer phase noise measured as a differential output to the phase
noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is
made using a balun. See Figure 1 on page 9.
Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS).
The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer
can then be calculated (via root-sum-square addition).
Frequency
(MHz)
156.25
Diff’l Input
Slew Rate
(V/ns)
1.0
Figure 13. Source Jitter (156.25 MHz)
Table 21. Source Jitter (156.25 MHz)
Source
Jitter
(fs)
38.2
Total Jitter
(SE)
(fs)
147.8
Additive Jitter
(SE)
(fs)
142.8
Total Jitter
(Diff’l)
(fs)
118.3
Additive Jitter
(Diff’l)
(fs)
112.0
Rev. 1.0
21