SI53312 Datasheet, PDF (24/33 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53312
2.12. Input Mux Noise Isolation
LVPECL output@156.25MHz;
Selected clk is active
Unselected clk is static
LVPECL output@156.25MHz;
Selected clk is static
Unselected clk is active
Mux Isolation = 61dB
Figure 16. Input Mux Noise Isolation
2.13. Power Supply Noise Rejection
The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low
jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and
SoCs and may reduce board-level filtering requirements. For more information, see AN491: “Power Supply
Rejection for Low Jitter Clocks”.
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Rev. 1.0