SI5355 Datasheet, PDF (21/22 Pages) Silicon Laboratories – ANY-FREQUENCY 1–200 MHZ QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5355
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
 Documentation updated to reflect CLKIN is on pin 4,
not pin 3.
Revision 0.2 to Revision 0.3
 Added cycle-cycle and phase jitter specifications to
Table 3 on page 5.
 Changed period jitter specification from 100 ps to
75 ps pk-pk.
 Added Theta JC specification to Table 5 on page 6.
 Updated "2. Typical Application Circuit" on page 7.
 Added Table 7 on page 9.
 Clarified device operation during an input clock loss
of signal.
 Updated Recommended PCB Layout.
Revision 0.3 to Revision 1.0
 Added shipment media information for GM (vs GMR)
parts.
 Changed Si5356 references to Si5355.
 Updated VDDO pin descriptions for unused clock
banks. VDDOx associated with an unused clock
bank should be tied to > 1.5 V.
 Changed the name of output enable/disable control
function pins in section 3.5 and Tables 3, 8, and 9 to
align better with the actual pin functionality.
 Updated Table 2. DC Characteristics.
Added IDDOx specification.
Corrected Pn Input Resistance specification.
 Updated Table 3, “AC Characteristics,” on page 5.
Added 10–90% input clock rise/fall time.
Added LOS assert/deassert time.
Added note on jitter test.
Updated 20–80% rise/fall time with C_L = 15 pF for
output clocks to the maximum value of 2.0 ns.
Changed Frequency Synthesis Resolution spec to the
correct value of 1ppb max.
 Updated recommended crystal parameters in
Table 4 on page 6 to show support for both crystals
rated for either 18 or 12 pF load capacitance.
 Updated Table 6 on page 6.
Added Soldering profile specification
Corrected Input Voltage Range (V_I2) to 1.3 V (max).
Added packaging/RoHS information.
 Removed jitter spec from section “3.9. Jitter
Performance” to prevent duplicating specs in
“Table 3. AC Characteristics.”
 Removed output-to-output skew spec from section
“3.8. CMOS Output Drivers” text to prevent
duplicating specs in “Table 3. AC Characteristics.”
 Added Evaluation Board information to the Ordering
Guide.
Revision 1.0 to Revision 1.1
 Updated ordering information to refer to revision B
silicon.
 Updated top marking explanation in Section 8.2
Rev. 1.1
21