SI5355 Datasheet, PDF (11/22 Pages) Silicon Laboratories – ANY-FREQUENCY 1–200 MHZ QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5355
3.5. Output Enable
Each of the device’s four banks of CMOS clock outputs can be individually disabled using OEB_A, OEB_B,
OEB_C, and OEB_D for CLK0/1, CLK2/3, CLK4/5, and CLK6/7, respectively. Alternatively, all clock outputs can be
disabled using the master output enable OEB_ALL. When a Si5355 clock output bank is disabled, both outputs are
driven to an active low state. When one or more banks of clock outputs are enabled or disabled, clock start and
stop transitions are handled glitchlessly.
3.6. Frequency Select/Device Reset
The device frequency plan is customized using the ClockBuilder web utility. The Si5355 optionally supports up to
three unique, pin-selectable configurations per device, enabling one device to replace up to three separate clock
ICs. To select a particular frequency plan, set the FS pins as outlined below:
For custom Si5355 devices configured to support two frequency plans, the FS1 pin should be set as shown in
Table 9:
Table 9. FS1 Pin Logic for 2 Profile Devices
FS1
Profile
0
1
1
2
For custom Si5355 devices configured to support three frequency plans, the FS1 and FS0 pins should be set as
shown in Table 10:
Table 10. FS1/FS0 Pin Logic for 3 Profile Devices
FS1
FS0
Profile
0
0
Reserved
0
1
1
1
0
2
1
1
3
If a change is made to the FS pin settings, the device reset pin (RESET) must be held high for the minimum pulse
width specified in Table 3 on page 5 to change the device configuration. The output clocks will be momentarily
squelched until the device begins operation with the new frequency plan.
If the RESET pin is not selected in ClockBuilder as one of the five programmable pins, a power-on reset must be
applied for an FS pin change to take effect.
3.7. Loss-of-Signal Alarm
The Si5355 includes an interrupt pin that monitors for both loss of PLL lock (LOL) and loss of input signal (LOS)
conditions. The LOS pin is asserted whenever LOL or LOS is true. The LOS condition occurs when there is no
input clock to the device. When an input clock is removed, the LOS pin will assert, and the output may drift up to
5%. The LOL condition occurs when there is a reference present but it is off in frequency by a significant amount.
In this condition, the LOS pin will assert and the output will be disabled. When the input clock with an appropriate
frequency is reapplied, the LOS pin will de-assert. Note that the LOS pin is an open-drain output.
Rev. 1.1
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