SI5355 Datasheet, PDF (1/22 Pages) Silicon Laboratories – ANY-FREQUENCY 1–200 MHZ QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5355
ANY-FREQUENCY 1–200 MHZ QUAD FREQUENCY
8-OUTPUT CLOCK GENERATOR
Features
 Generates any frequency from 1 to
 Excellent PSRR performance
200 MHz on each of the 4 output banks
eliminates need for external power
 Eight CMOS clock outputs
supply filtering
 Guaranteed 0 ppm frequency synthesis ^{ Low power: 45 mA (core)}
error for any combination of frequencies  Core VDD: 1.8, 2.5, or 3.3 V
 25 or 27 MHz xtal or 5–200 MHz input clk  Separate VDDO for each bank of
 Five programmable control pins (output
outputs: 1.8, 2.5, or 3.3 V
enable, frequency select, reset)
 Small size: 4x4 mm 24-QFN
 Separate OEB pins to disable individual  Industrial temperature range:
banks or all outputs
–40 to +85 °C
 Loss of signal output
 Custom versions available using
 Low 50 ps (typ) pk-pk period jitter
ClockBuilder™ web utility
 Phase jitter: 2 ps rms 12 kHz–20 MHz ^{ Samples available in 2 weeks}
Applications
Ordering Information:
See page 17.
Pin Assignments
 Printers
 Audio/video
 Networking
 Communications
 Storage
 Switches/routers
 Computing
 Servers
 OC-3/OC-12 line cards
Description
The Si5355 is a highly flexible clock generator capable of synthesizing four
completely non-integer related frequencies up to 200 MHz. The device has four
banks of outputs with each bank supporting two CMOS outputs at the same
frequency. Using Silicon Laboratories' patented MultiSynth fractional divider
technology, all outputs are guaranteed to have 0 ppm frequency synthesis error
regardless of configuration, enabling the replacement of multiple clock ICs and
crystal oscillators with a single device. Through a flexible web configuration utility
called ClockBuilder™ (www.silabs.com/ClockBuilder), factory-customized pin-
controlled Si5355 devices are available in two weeks without minimum order
quantity restrictions. The Si5355 supports up to three independent, pin-selectable
device configurations, enabling one device to replace three separate clock ICs.
Top View
24 23 22 21 20 19
XA 1
18 CLK2
XB 2
17 CLK3
P1 3
CLKIN 4
GGNNDD
16 VDDOB
15 VDDOC
P4 5
14 _CLK4
P5 6
7
13 _CLK5
8 9 10 11 12
Functional Block Diagram
Rev. 1.1 1/13
Copyright © 2013 by Silicon Laboratories
Si5355