SI5355 Datasheet, PDF (16/22 Pages) Silicon Laboratories – ANY-FREQUENCY 1–200 MHZ QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5355
17
18
19
20
21
22
23
24
GND
PAD
CLK3
CLK2
P3
VDDOA
CLK1
CLK0
GND
VDD
GND
Table 11. Si5355 Pin Descriptions (Continued)
O Output Clock 3.
CMOS output clock. If unused, this pin must be left floating.
O Output Clock 2.
CMOS output clock. If unused, this pin must be left floating.
I Multi-Function Input (3.3 V Tolerant).
This pin functions as a multi-function input pin. The pin function (OEB_ALL, OEB_A,
OEB_B, OEB_C, OEB_D, Frequency Select, or Reset) is user-selectable at time of
configuration using the ClockBuilder configuration utility
VDD Clock Output Bank A Supply Voltage.
Power supply for clock outputs 0 and 1. May be operated from a 1.8, 2.5, or 3.3 V sup-
ply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK0/1 are not
used, this pin must be tied to VDD or a voltage rail of at least 1.5 V.
O Output Clock 1.
CMOS output clock. If unused, this pin must be left floating.
O Output Clock 0.
CMOS output clock. If unused, this pin must be left floating.
GND Ground.
Must be connected to system ground. Minimize the ground path impedance for optimal
performance of the device.
VDD Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should
be located very close to this pin.
GND Ground Pad.
This is the large pad in the center of the package. See"7. Recommended PCB Layout"
on page 19 for the PCB pad sizes and ground via requirements. The device will not
function unless the ground pad is properly connected to a ground plane on the PCB.
16
Rev. 1.1