SI5355 Datasheet, PDF (13/22 Pages) Silicon Laboratories – ANY-FREQUENCY 1–200 MHZ QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5355
3.9. Jitter Performance
The Si5355 provides consistently low jitter for any combination of output frequencies. The device leverages a low
phase noise single PLL architecture and Silicon Laboratories’ patented MultiSynth fractional output divider
technology to deliver excellent jitter performance guaranteed across process, temperature, and voltage. The
Si5355 provides superior performance to conventional multi-PLL solutions which may suffer from degraded jitter
performance depending on frequency plan and the number of active PLLs.
3.10. Power Supply Considerations
The Si5355 has 2 core supply voltage pins (V_DD) and 4 clock output bank supply voltage pins (V_DDOA–V_DDOD),
enabling the device to be used in mixed supply applications. The Si5355 does not require ferrite beads for power
supply filtering. The device has extensive on-chip power supply regulation to minimize the impact of power supply
noise on output jitter. Figure 6 is a curve of additive phase jitter with power supply noise. Note that even when a
significant amount of noise is applied to the device power supply, additive phase jitter is still very small.
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0
0.0001
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VDDO
VDD
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Modulation Frequency (MHz)
Figure 6. Peak-to-Peak Additive Phase Jitter from 100 mV Sine Wave on Supply
3.11. ClockBuilder Web-Customization Utility
ClockBuilder is a web-based utility available at www.silabs.com/ClockBuilder that allows hardware designers to
tailor the Si5355’s flexible clock architecture to meet any application-specific requirements and order custom clock
samples. Through a simple point-and-click interface, users can specify any combination of input frequency and
output frequencies and generate a custom part number for each application-specific configuration. There are no
minimum order quantity restrictions.
ClockBuilder enables mass customization of clock generators. This allows a broader range of applications to take
advantage of using application-specific pin controlled clocks, simplifying design while eliminating the firmware
development required by traditional I²C-programmable clock generators.
Based on Silicon Labs’ patented MultiSynth technology, the device PLL output frequency is constant and all clock
output frequencies are synthesized by the four MultiSynth fractional dividers. All PLL parameters, including divider
settings, VCO frequency, loop bandwidth, charge pump current, and phase margin are internally set by the device
during the configuration process. This ensures optimized jitter performance and loop stability while simplifying
design.
Rev. 1.1
13