SI5355 Datasheet, PDF (15/22 Pages) Silicon Laboratories – ANY-FREQUENCY 1–200 MHZ QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5355
Table 11. Si5355 Pin Descriptions (Continued)
5
P4
I Multi-Function Input.
This pin functions as a multi-function input pin. The pin function (OEB_ALL, OEB_A,
OEB_B, OEB_C, OEB_D, or Reset) is user-selectable at time of configuration using the
ClockBuilder configuration utility. A resistor voltage divider is required when controlled
by a signal greater than 1.3 V. See “2. Typical Application Circuit” for details.
6
P5
I Multi-Function Input.
This pin functions as a multi-function input pin. The pin function (OEB_ALL, OEB_A,
OEB_B, OEB_C, OEB_D, or Reset) is user-selectable at time of configuration using the
ClockBuilder configuration utility. A resistor voltage divider is required when controlled
by a signal greater than 1.3 V. See “2. Typical Application Circuit” for details.
7
VDD VDD Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should
be located very close to this pin.
8
LOS
O Loss of Signal.
A typical pullup resistor of 1–4 k should be used on this pin.
This pin functions as an input clock signal status pin.
0 = no LOS or LOL condition
1 = LOS or LOL condition
This pin is open drain and requires an external >1 k pullup resistor.
9
CLK7
O Output Clock 7.
CMOS output clock. If unused, this pin must be left floating.
10
CLK6
O Output Clock 6.
CMOS output clock. If unused, this pin must be left floating.
11 VDDOD VDD Clock Output Bank D Supply Voltage.
Power supply for clock outputs 6 and 7. May be operated from a 1.8, 2.5, or 3.3 V sup-
ply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK6/7 are not
used, this pin must be tied to VDD or a voltage rail of at least 1.5 V.
12
P2
I Multi-Function Input (3.3 V Tolerant).
This pin functions as a multi-function input pin. The pin function (OEB_ALL, OEB_A,
OEB_B, OEB_C, OEB_D, or Frequency Select) is user-selectable at time of configura-
tion using the ClockBuilder configuration utility
13
CLK5
O Output Clock 5.
CMOS output clock. If unused, this pin must be left floating.
14
CLK4
O Output Clock 4.
CMOS output clock. If unused, this pin must be left floating.
15 VDDOC VDD Clock Output Bank C Supply Voltage.
Power supply for clock outputs 4 and 5. May be operated from a 1.8, 2.5 or 3.3 V sup-
ply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK4/5 are not
used, this pin must be tied to VDD or a voltage rail of at least 1.5 V.
16 VDDOB VDD Clock Output Bank B Supply Voltage.
Power supply for clock outputs 2 and 3. May be operated from a 1.8, 2.5, or 3.3 V sup-
ply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK2/3 are not
used, this pin must be tied to VDD or a voltage rail of at least 1.5 V.
Rev. 1.1
15