S-1701 Datasheet, PDF (43/70 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION

HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION
Rev.2.4_00
S-1701 Series
(1) (2)
Hysteresis width (V_HYS)
A
(3) (4) (5)
B
V_DD
Release voltage (+V_DET)
Detection voltage (−V_DET)
Minimum operating voltage
V_SS
V_IN (V_SENSE)
V_SS
Output from VDOUT pin
t_D
Remark The above figure shows the case when the SENSE pin is connected to VIN.
Figure 37 Operation
2. Delay circuit
The delay circuit delays the output signal from the time when the SENSE voltage (V_SENSE) exceeds
the release voltage (+V_DET) when V_SENSE is turned on (refer to point B in Figure 37). The output
signal is not delayed when V_SENSE goes below the detection voltage (−V_DET) (refer to point A in
Figure 37).
The delay time (t_D) is a fixed value that is determined by a built-in clock generator which consists of
constant current an a capacitor, and counter.
3. Delay circuit output voltage detection type (S-1701 Series D/ E/ F/ K/ L/ M/ U/ V/ W types)
If the input voltage or load current changes transiently, an undershoot or overshoot occurs in the
output voltage of the regulator. In the product types in which the output voltage of the regulator is
detected by the detector, if the output voltage is the detection voltage or lower due to the undershoot,
the detector operates and a reset signal may be output. To prevent this, set the value of the input-
and-output capacitor of a regulator so that the undershoot is the minimum value or set a voltage
range that allows the difference between the output voltage and detection voltage to be equal to or
greater than the undershoot.
Seiko Instruments Inc.
43