S-1701 Datasheet, PDF (40/70 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION

HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION
S-1701 Series
Rev.2.4_00
„ Operation
Regulator block
1. Basic operation
Figure 34 shows the block diagram of the regulator block.
The error amplifier compares the reference voltage (V_ref) with V_fb, which is the output voltage resistance
divided by feedback resistors R_s and R_f. It supplies the output transistor with the gate voltage necessary
to ensure a certain output voltage free of any fluctuations of input voltage and temperature.
Output voltage is selectable from the range of 1.5 to 5.0 V in the S-1701 Series.
VIN
Current
supply
V_ref
Error amplifier
−
+
Reference
voltage circuit
*1
R_f
V_fb
R_s
VOUT
VSS
*1. Parasitic diode
Figure 34 Block Diagram (Regulator Block)
2. Output transistor
The S-1701 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that V_OUT does not exceed V_IN + 0.3 V to prevent the voltage regulator from being damaged due to
inverse current flowing from the VOUT pin through a parasitic diode to the VIN pin.
40
Seiko Instruments Inc.